Formal analysis of fault tolerant algorithms in the time-triggered architecture
نویسنده
چکیده
Formal Model Layers The basis for the formal analysis work has been given in Chapter 2. It introduces adequate formal models to analyse distributed algorithms at different levels of abstraction. We have presented a formalization of the untimed synchronous system model, and a ground model for time-triggered systems. In particular, we have introduced abstract models of the communication network that capture the essence of the TDMA communication mechanism and encompass both the star-coupler approach and the bus topology. It has been demonstrated that the different guardian systems used in these two topologies, the central guardians and the local bus guardians, respectively, can be regarded as instances of a common, abstract scheme. The relationship of the formal models has been described in Chapter 5. It has been shown that the internal states of the processors as seen in the abstract, untimed synchronous system level soundly correspond to the states of the processors on the time-triggered level during the global communication phase of a slot. The prerequisite for this refinement is that the clocks of the processors are synchronized within a small bounded quantity. Both the formalizations of the synchronous and time-triggered system models and the corresponding refinement proof are based on developments by J. Rushby [Rus99]. We have extended the work in two respects. In particular, we have augmented the formalizations with a series of generic models to describe the behaviour and functionality of the communication network and the guardians. Moreover, the description of sending and receiving messages has been separated from the timing concerns in the time-triggered model for two reasons. First, we needed a different way to model send and receive faults of processors that is more appropriate for TTP/C’s communication through broadcast channels. Second, the separation allows the same fault models for an algorithm to be used on both the untimed synchronous and the time-trigerred system level and thus ultimately facilitates the integration of the models for group mem-
منابع مشابه
Systematic Formal Verification for Fault-Tolerant Time-Triggered Algorithms
Many critical real-time applications are implemented as time-triggered systems. We present a systematic way to derive such time-triggered implementations from algorithms specified as functional programs (in which form their correctness and fault-tolerance properties can be formally and mechanically verified with relative ease). The functional program is first transformed into an untimed synchro...
متن کاملFormal Modelling and Analysis of Fault Tolerance Proper- Ties in the Time-triggered Architecture
The Time-Triggered Architecture is a distributed computer architecture for the implementation of highly dependable real-time systems specifically targeting embedded applications, such as digital control systems in the automotive and avionics domain. We have formally modelled and analysed various aspects of the underlying communication protocol TTP/C and its fault tolerance properties. This pape...
متن کاملAn Overview of Formal Verification for the Time-Triggered Architecture
We describe formal verification of some of the key algorithms in the Time-Triggered Architecture (TTA) for real-time safety-critical control applications. Some of these algorithms pose formidable challenges to current techniques and have been formally verified only in simplified form or under restricted fault assumptions. We describe what has been done and what remains to be done and indicate s...
متن کاملExpanded Version of a Paper from the Sixth Working Conference on Dependable Computing for Critical Applications, Systematic Formal Veriication for Fault-tolerant Time-triggered Algorithms
Many critical real-time applications are implemented as time-triggered systems. We present a systematic way to derive a time-triggered implementation from a fault-tolerant algorithm speciied as a functional program. It is relatively easy to formally and mechanically verify correctness and fault-tolerance properties of algorithms expressed in this latter form. The functional program is next tran...
متن کاملA generalized ABFT technique using a fault tolerant neural network
In this paper we first show that standard BP algorithm cannot yeild to a uniform information distribution over the neural network architecture. A measure of sensitivity is defined to evaluate fault tolerance of neural network and then we show that the sensitivity of a link is closely related to the amount of information passes through it. Based on this assumption, we prove that the distribu...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2003